This invention relates to logic circuits utilizing metal oxide semiconductor field-effect transistors, and more particularly to complementary set-reset logic circuits utilizing both pMOS and nMOS devices on the same chip in a complementary (cMOS) circuit.
A number of logic forms and clocking schemes for cMOS integrated circuits are in common use. The most common logic form consists of two networks of transistors, the gates of which are connected to the input variables. An n-channel network defines the Boolean condition under which the output is connected to ground (logic zero), and a p-channel network defines the complementary condition under which the output is connected to a logical one. Since in many cMOS processes the output of a single pass transistor cannot be guaranteed to exceed the logic threshold of a typical inverter, pass transistor networks are either forbidden or a complementary transmission gate employing both p and n-channel devices is used.
Clocking schemes for cMOS presently offer tradeoffs over a wide range in the risk vs efficiency space. In one scheme, a single phase clock and its complement are distributed, and used to control either transmission gates or transistors controlling power to the p and n-channel switching networks. Proper operation in either case requires that the logic delay of the stage exceed the skew between the two clock lines. In a much safer approach, a two-phase clock is used, both the clock and its complement being distributed for each phase. In this case risk is eliminated at the expense of doubling the clock wiring. Yet another form is popular in gate level designs. A single clock is distributed, and locally inverted at master-slave storage elements. Risk in this case is eliminated at the expense of a minimum storage element employing ten or more transistors.